Job Description:
Lead and coordinate a small team of mixed-signal ASIC design engineers
Design of advanced mixed-signal circuits data converters, sub-sampling phase locked loops, serdes and building blocks for RF CMOS, data communication and low-power & low-voltage applications. implement new mixed signal IP and IC solutions.
Achieve successful realization of the layout in close collaboration with layout team.
Work with application developers to co-develop hardware and software systems.
Collaborate with teams in India and abroad during project implementation phase.
Requirements:
M.Tech / PhD degrees from top universities
+ 10 years’ experience industrial experience in analog and mixed-signal design.
Successful realization of more than 5 ASIC designs
Knowledge and Experience with HDL languages Verilog and/or VHDL.
Proficiency in system and behavioural modeling using MATLAB, System Verilog, Verilog-A/AMS.
Scripting skills: Python, Perl and C shell.
Must have a previous experience of taking multiple mixed-signal ICs through the entire development cycle, from concept to production.
Experience with design, implementation, and development environments for reconfigurable systems (such as FPGAs) is a plus.
Experience with the silicon manufacturers and working with various CMOS process technologies.
Experience: 10 years +
Ability to work in a team and independently
Ability to adapt to a diverse customer base and willingness to undertake periodic local
Travel to customer sites
Aptitude for learning new technologies and applications
Good writing, verbal and interpersonal communication skills
Competent in developing solutions as well as identifying problems
Knowledge of production processes to ensure quality and robustness